High speed memories have conventionally utilized bipolar technology due to the low source impedance of bipolar transistors as opposed to use of MOS transistors which provide a nonlinear resistance for driving various nodes and output lines. Pure MOS memories are relatively slow with respect to access time as compared to bipolar memories. This is due to the fact that high density memories have a large number of transistors which are interconnected by long lengths of line which have a relatively high capacitance associated therewith. However, MOS memories have a significant advantage over bipolar memories in that they draw very low current.
In order to improve the access time of an MOS memory, bipolar devices have been combined with MOS devices to provide a low source impedance to drive various output or high capacitance nodes. However, when combining bipolar and CMOS transistors on the same integrated circuit, it is necessary that the voltages that control the various transistors be compatible. For example, bipolar transistors utilizing emitter coupled logic (ECL) require a very small voltage swing whereas MOS devices require rather large voltage swings to insure proper operating characteristics.
Generally, specifications for high speed memories require compatibility with ECL levels. Therefore, when MOS technology is incorporated into a high speed bipolar device, translation circuits are utilized to interface between the ECL circuitry and the MOS circuitry. For example, in an ECL memory, the input and output of all the address lines to the package would require ECL compatibility. When an MOS memory cell which would provide low current is utilized, translation circuits internal to the package are required to convert the ECL voltage swings to the much higher voltage swing required for MOS circuitry. This can be a disadvantage due to the larger amount of circuitry required to perform the translation, which circuitry would inherently have a predetermined amount of delay and also consume additional current.
Since the purpose of incorporating MOS transistors into a high speed memory is to minimize power consumption, the use of translation circuits would detract somewhat from the realized advantages. A further disadvantage exists in the size of the MOS memory cells which are usually rather large due to the requirement that the MOS transistors must drive large capacitive loads. In order to provide the appropriate drive at a reasonable operating speed, the size of the MOS transistors is increased to lower the series resistance or source impedance of that transistor. This results in an overly large cell which, in addition to the additional circuitry required for the translation, requires a proportionally large amount of silicon area to realize a practical memory cell with MOS transistors.